An electrical circuit (e.g., chip, die, integrated circuit, etc.) is one of the most essential hardware foundations of modern information society. Different electrical circuits can be connected into an interconnection system by channel(s), so these electrical circuits can exchange signals (e.g., information, data, messages, commands and/or packages) to coordinate and cooperate with each other for implementing integrated macro functions. However, the characteristics of the channel will impact the quality of signal exchange. Generally, the channel is of low-pass nature, and therefore will suppress high-frequency portion of the signal and cause signal distortion. For example, when an electrical circuit acts as a transmitter and transmits a signal of a square waveform to another electrical circuit which acts as a receiver, the receiver will receive a slowly rising and falling waveform, instead of a square waveform with sharp rising and falling edges. In the waveform received by the receiver, the slowly rising portion is referred to as a pre-cursor, the peak of slowly rising forms a main cursor, and the slowly falling portion after the peak is referred to as a post-cursor. Signal distortion will cause inter-symbol interference (ISI) and degrade the quality of signal transmission, e.g., increase bit error rate.
To compensate the impact of the channel, the transmitter and the receiver are respectively equipped with filtering and equalization mechanisms. For example, the filtering mechanism of the transmitter (Tx) can include a pre-emphasis filter for emphasizing the high-frequency portion of the signal of the transmitter, and the equalization mechanism of receiver (Rx) can include a CTLE (continuous time linear equalizer) and a DFE (decision feedback equalizer). When a transmitter intends to send a signal to a receiver, the filter of the transmitter will filter the outgoing signal based on a plurality of filter taps, so the filtered signal can be driven to a channel. When the receiver receives the incoming signal from the channel, the receiver will equalize the received signal based on a plurality of equalizer taps, and then retrieve the contents and/or other information (e.g., clock) from the equalized signal.
FIG. 1 is a schematic circuit diagram illustrating a conventional Serdes. In the electrical circuit of a transmitter (Tx), a pre-emphasis filter receives a data signal S and generates a filtered data signal Sw. In particular, the pre-emphasis filter 102 increases the magnitude of the high-frequency portion of the data signal S and thus generates the filtered data signal Sw.
After the filtered data signal Sw is transmitted from a first end of a channel 104 to a second end of the channel 104, the filtered data signal Sw is turned into a received signal Sx and inputted into the electrical circuit of a receiver Rx. In the electrical circuit of the receiver Rx, a clock data recovering system 110 is used to reconstruct the data signal S.
The clock data recovering system 110 comprises a data sampler 113, an edge sampler 115, a clock data recovering circuit 117, a decision feedback equalizer 119 and an adder 111.
Generally, the received signal Sx from the second end of the channel 104 is inputted into the clock data recovering system 110. By the adder 111, a feedback equalization signal Sf from the decision feedback equalizer 119 and the received signal Sx are superposed with each other to generate a superposed signal Sz.
The data sampler 113 samples the superposed signal Sz according to a data clock dCLK and thus generates a sampled data signal Sd. Moreover, the edge sampler 115 samples the superposed signal Sz according to an edge clock eCLK and thus generates a sampled edge signal Sedg.
The clock data recovering circuit 117 receives the sampled data signal Sd and the sampled edge signal Sedg and thus generates the data clock dCLK and the edge clock eCLK. The decision feedback equalizer 119 receives the sampled data signal Sd and thus generates the feedback equalization signal Sf.
As mentioned above, the clock data recovering system 110 is used for sampling the data and the data edge of the superposed signal Sz and generating the data clock dCLK and the edge clock eCLK by using the clock data recovering circuit 117. In this kind of clock data recovering system 110, the clock data recovering circuit 117 has to generate the data clock dCLK and the edge clock eCLK at double data rate in order to over-sample the superposed signal Sz. Moreover, the phase difference between the data clock dCLK and the edge clock eCLK is 180 degrees.
In particular, the clock data recovering circuit 117 further comprises a bang-bang phase detector for receiving the sampled data signal Sd and the sampled edge signal Sedg and generating a phase update information. According to the phase update information, the phases of the data clock dCLK and the edge clock eCLK are correspondingly adjusted.
Obviously, the conventional Serdes is not suitably applied to a high speed data transmission system. For example, if the data rate of the data signal S is 16 Gbps, it is necessary for the clock data recovering circuit 117 to generate the data clock dCLK and the edge clock eCLK at double data rate (e.g. 32 GHz) in order to reconstruct the data signal S.